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Bacellar, A., Susskind, Z., Breternitz Jr., M., John, E., John, L., Lima, P....França, F. (2024). Differentiable weightless neural networks. In Salakhutdinov R., Kolter Z., Heller K., Weller A., Oliver N., Scarlett J., Berkenkamp F. (Ed.), Proceedings of the 41st International Conference on Machine Learning, PMLR. (pp. 2277-2295). Vienna: ML Research Press.
A. T. Bacellar et al., "Differentiable weightless neural networks", in Proc. of the 41st Int. Conf. on Machine Learning, PMLR, Salakhutdinov R., Kolter Z., Heller K., Weller A., Oliver N., Scarlett J., Berkenkamp F., Ed., Vienna, ML Research Press, 2024, vol. 235, pp. 2277-2295
@inproceedings{bacellar2024_1782623309503,
author = "Bacellar, A. and Susskind, Z. and Breternitz Jr., M. and John, E. and John, L. and Lima, P. and França, F.",
title = "Differentiable weightless neural networks",
booktitle = "Proceedings of the 41st International Conference on Machine Learning, PMLR",
year = "2024",
editor = "Salakhutdinov R., Kolter Z., Heller K., Weller A., Oliver N., Scarlett J., Berkenkamp F.",
volume = "235",
number = "",
series = "",
pages = "2277-2295",
publisher = "ML Research Press",
address = "Vienna",
organization = "",
url = "https://proceedings.mlr.press/v235/bacellar24a.html"
}
TY - CPAPER TI - Differentiable weightless neural networks T2 - Proceedings of the 41st International Conference on Machine Learning, PMLR VL - 235 AU - Bacellar, A. AU - Susskind, Z. AU - Breternitz Jr., M. AU - John, E. AU - John, L. AU - Lima, P. AU - França, F. PY - 2024 SP - 2277-2295 SN - 2640-3498 CY - Vienna UR - https://proceedings.mlr.press/v235/bacellar24a.html AB - We introduce the Differentiable Weightless Neural Network (DWN), a model based on interconnected lookup tables. Training of DWNs is enabled by a novel Extended Finite Difference technique for approximate differentiation of binary values. We propose Learnable Mapping, Learnable Reduction, and Spectral Regularization to further improve the accuracy and efficiency of these models. We evaluate DWNs in three edge computing contexts: (1) an FPGA-based hardware accelerator, where they demonstrate superior latency, throughput, energy efficiency, and model area compared to state-of-the-art solutions, (2) a low-power microcontroller, where they achieve preferable accuracy to XGBoost while subject to stringent memory constraints, and (3) ultralow-cost chips, where they consistently outperform small models in both accuracy and projected hardware area. DWNs also compare favorably against leading approaches for tabular datasets, with higher average rank. Overall, our work positions DWNs as a pioneering solution for edge-compatible high-throughput neural networks. ER -
English