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Santos, D., Joao Cabacinho, Casaleiro, J., Leithardt, V. R. Q. & Oliveira, L. B. (2026). AES hardware architectures and non-standard Rijndael extensions up to 1024-bit keys: An open-source FPGA and 45-nm ASIC evaluation. Journal of Systems Architecture, 181. https://doi.org/10.1016/j.sysarc.2026.104028

D. Santos et al.,  "AES hardware architectures and non-standard Rijndael extensions up to 1024-bit keys: An open-source FPGA and 45-nm ASIC evaluation", in Journal of Systems Architecture, vol. 181, 2026

@article{santos2026_1793070927513,
	author = "Santos, D. and Joao Cabacinho and Casaleiro, J. and Leithardt, V. R. Q. and Oliveira, L. B.",
	title = "AES hardware architectures and non-standard Rijndael extensions up to 1024-bit keys: An open-source FPGA and 45-nm ASIC evaluation",
	journal = "Journal of Systems Architecture",
	year = "2026",
	volume = "181",
	number = "",
	doi = "10.1016/j.sysarc.2026.104028",
	url = "https://www.sciencedirect.com/journal/journal-of-systems-architecture"
}

TY  - JOUR
TI  - AES hardware architectures and non-standard Rijndael extensions up to 1024-bit keys: An open-source FPGA and 45-nm ASIC evaluation
T2  - Journal of Systems Architecture
VL  - 181
AU  - Santos, D.
AU  - Joao Cabacinho
AU  - Casaleiro, J.
AU  - Leithardt, V. R. Q.
AU  - Oliveira, L. B.
PY  - 2026
SN  - 1383-7621
DO  - 10.1016/j.sysarc.2026.104028
UR  - https://www.sciencedirect.com/journal/journal-of-systems-architecture
AB  - Recent advances in embedded and IoT systems demand scalable and efficient cryptographic hardware capable of balancing performance, area, and energy constraints.
This paper presents a unified hardware evaluation of the standardized AES-128, AES-192, and AES-256 configurations together with two non-standard, author-defined extended Rijndael configurations using 512 and 1024-bit keys, targeting both application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Six micro-architectures are considered: fully iterative, two round partially unrolled, fully pipelined and their composite-field S-box variants. All designs share a 128-bit datapath and differ only in round reuse, enabling a controlled study of how the number of rounds and the key schedule depth affect area, maximum clock frequency, throughput, latency and area efficiency (Gbps/mm2). The ASIC flow uses an open-source RTL to gates methodology in a 45 nm standard-cell library. The same RTL is mapped to a ECP5 FPGA to compare LUT usage and achievable frequency under realistic routing constraints. All RTL sources, synthesis scripts and configuration files used in this work are compatible with publicly available open-source EDA tools, enabling full reproducibility of the presented results.
ER  -