Weightless neural networks (WNNs) are a type of neural model which use random access memory (RAM) to determine neuron activation, as opposed to weights and dot products commonly used in modern deep learning approaches. This makes WNN attractive for a class of applications wherein the computational load (and energy requirements) is limited due to device size, cost or battery lifetimes. Within processors there is a need for efficient prediction of upcoming events, such as branch prediction, cache tag miss/mit, as well as SOC-wide events that control voltage and frequency for efficient power management. The reduced requirements in hardware cost and memory size make WNNs well suited for this applications. We describe recent results indicate the suitability for WNN in branch prediction at reduced memory requirements.

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microarchitectural predictor,CPU,neural networks